1. Field of the Invention
This invention relates generally to timing analysis techniques, and more particularly to a method, of implementing static timing analysis associated with System-on-chips (SoCs).
2. Description of the Prior Art
Today's SoCs consist of several million gates of equivalent logic and memory running at high clock frequencies. This results in considerable voltage drop from periphery to the center of the chip for wire bond designs for both functional (or “mission mode”) and test modes. These voltage drops are seen to be worse in the case of test modes, as almost all the flops are switching simultaneously. Techniques have been devised to minimize voltage drop in the test mode. Such methods however, generally increase test time which adversely impacts the bottom line.
At present, to compensate for voltage drop, designs are built with margins for timing closure. Each static timing analysis (STA) run is typically done at a PVT (process, voltage, temperature) corner using flat timing margins. This technique results in extra gates on the die. Further, a question remains as to whether enough margin exists to compensate for the voltage drop. Voltage drop is becoming more critical for timing analysis with decreasing core voltages and increasing clock frequencies associated with modern products and applications. Further, voltage drops are not necessarily identical for functional and test modes. Design margins therefore, must comprehend the worst case scenario.
IR drop analysis today is pessimistic, which results in additional margins that increase cycle times for timing closure and potentially increases die size. Further, today's design flow does not comprehend dynamic voltage drop.
In view of the foregoing, it would be highly desirable and advantageous to provide a timing closure analysis technique for SoCs that uses a more realistic scenario by accounting for impact of both dynamic/static voltage drops on delays and not just rely on static IR drops.